With the rapid use of integrated circuit memories and various types of PROM memories, considerable efforts have been made to establish the reliability of such devices and to inspect and test production multitudes of such devices with efforts that are reasonable in time and cost.
In the prior and existing arts, semi-conductor memory devices have been tested with long, expensive and costly procedures whereby a computer is programmed to address all possible data combinations in the tested-memory and then using a previously stored standard of what data should be in the memory, then to make individual comparisons of the standard against each data bits in the tested memory. This required the use of a main computer and main memory, in addition to special programming procedures which were very costly and further required relatively long time periods to exercise the memory and to check all of its internal data with an external standard.
The use of semi-conductor memories and PROMs particularly involves a multi-million dollar industry that is continuously expanding. The use of millions of said semi-conductor memories not only brings up problems of production, but especially of testing that production, to see if the produced items are workable and reliable and especially how quickly the memories can respond (access time) with stable output of accessed data.
Many attempts have been made to handle the problem of weeding out defective PROMs and estabilishing their access time or speed of response. When defective uncalibrated PROMs get into the production line, they involve systems which can cause untold losses in terms of down time, production loss, customer upset and debugging problems. It is necessary that there be some way of eliminating defective PROMs using minimal testing time in order to save millions of dollars in repairing, debugging and rebuilding systems which might arise from defective or slow PROMs.
Thus, much effort and expense has been devoted to the testing and calibration of the response time of semi-conductor memories. And the expense of such testing can sometimes become almost prohibitive when it requires special programming, special computer apparatus, and long periods of operation time in order to test a single memory or a group of memories.
The herein described apparatus and technique for testing of semi-conductor memories involves a very minimal cost of apparatus and provides an automatic test procedure which steps through a series of "access times" of diminishing values (done for each bit accessed from the memory being tested). Upon the first detection of instability or access error, the test cycle is shut off and a display readout is made of the "reliable" time period of access. This permits the tested memory to be identified as to its lowest reliable access time period and below which there is no reliability. The unit described herein can test reliability of memories down to "access time" periods of a few nanoseconds.